About this job

Sapienza Consulting, a Serco company, is recruiting a Micro-Electronics Engineer for Sapienza specialized in digital signal processing and microelectronics to work on our Customers Site (ESA-ESTEC).

Sapienza has been a partner of ESA for almost 30 years and we pride ourselves in supporting a wide range of missions including Galileo, MTG, Copernicus and ExoMars. We are one of the leading space industry and services companies who is a trusted adviser to international and national space agencies across the globe.

Responsibilities

• Provision of VLSI (ASIC & FPGA) technical expertise to Projects involving requirements analysis, performance and budgets analysis, writing and assessment of VLSI specifications; review, evaluation and checking of industrial contractor’s VLSI designs. Identification of design deficiencies and problem areas and proposals for their solutions.
• Design, analysis, verification of VLSI systems for control and data processing applications, and/or signal processing using industrial standard tools, hardware description and programming languages.
• Technical and administrative management of the ESA SystemC and synthesizable VHDL IP Core pool of designs. This work will involve: optimization, update and overall maintenance and of the ESA VHDL IP Cores databases, provision of technical support to ESA IP Cores users (performing analysis and finding solutions to problems in VHDL code, documentation or design methodology) holding a strong collaboration with our Contracts department in arranging and solving licenses and patent issues. Advertising the ESA IP service (website, workshops, etc.), handling IP cores requests and their distribution.
• The employee will support ASIC and/or FPGA technology developments for R&D and /or projects, supervising that good design practices and manufacturing and test methodologies are applied. In addition, independent verification (through code inspection, simulation and timing analysis) and validation (through HW tests) will have to be carried out for some ASIC and FPGAS developments.
• When asked to support development contracts regarding the above areas, act as the activity technical responsible, maintain interfaces with the prime contractors, participate in progress meetings and reviews, as requested, and provide appropriate feedback on the achieved progress and discussions.
• When supporting projects, interface with ESA’s project teams, the prime and lower level contractors, participate in progress meetings and reviews, as requested by project work, and provide appropriate feedback on the achieved progress and discussions.

Profile

• Master’s degree in Electronics Engineering or Physics, specialized in digital signal processing and microelectronics, with five or more years of experience in at least three of the following domains:
  • development of digital signal processing architecture, simulation, implementation and validation, including the coding into a hardware description language (HDL).
  • development of functional and performance test cases and benches for the verification, profiling and validation of the digital signal processing architecture.
  • design and test of digital FPGAs and ASICs (specifications, block design, top level integration, design for test, pre and post layout simulation and timing analysis, gates synthesis, support during layout, prototype test and in system validation), with proficiency in HDL (VHDL, Verilog and System-C).
  • VLSI IC Design CAD tools such as: Synopsys, CADENCE, Mentor, MATLAB and/or Simulink as well as hardware description languages (VHDL, Verilog, SystemVerilog, SystemC, …).
  • FPGA HW and SW of several vendors such as: Xilinx, Microchip (former Microsemi, former ACTEL) and/or NanoXplore.
  • preparation of digital FPGA and ASIC design test-benches, for functional verification, validation and electrical characterization, using signal generators, oscilloscopes and signal analyzers.
  • system administration in UNIX and Windows for IC Design CAD tools.
• strong foundations in mathematics, linear algebra, physics and signal processing intuition regarding time/frequency duality, implications of discrete time signal processing, and implementation details on fixed/floating point architectures.
• knowledge of space wireless and wireline communications systems, standards, including physical, data link, network and transport layer design for Spacewire, SpaceFibre, CAN, PCIe, JESD204B/C, Ethernet, IEEE 802.15(a).
• knowledge of encoding and decoding, forward error correction (FEC) blocks, interleaving, digital pre-distortion, modulation and demodulation (PSK, PAM, QAM, OFDM, etc), spreading and dispreading, encryption and decryption and link budget.
• knowledge of converters, baseband sampling, direct digital conversion, digital filters, fast fourier transforms, feature extraction, estimation, decision-making, detection, acquisition, tracking and adaptive control.
• knowledge of standard interfaces architectures: Spacewire, SpaceFibre, PCIe, Ethernet, JESD204B/C, SerDes (NRZ, PAM4), AMBA, AXI, DDR, etc.
• experience in developing automated, self-checking test benches, UVM and/or UVVM.
• experience with VHDL-AMS, Verilog-AMS mixed-signal hardware description language.
• experience with Microprocessors (e.g. SPARC, ARM, RISC-V) and HW-SW co-design.
• experience with mitigation of radiation effects and/or radiation tests of FPGAs and/or ASICs.
• knowledge of the Space environment, its effects on microelectronics devices and related technology, as well as ECSS quality standards applied to space VLSI ICs.
• experience with using third party Intellectual Property (IP) designs (in VHDL and/or SystemC) is a requirement.
• comfortable with working in a diverse and multinational team environment.
• excellent interpersonal skills are needed, together with a high degree organizational and communication abilities.
• proficient in the English language, both written and spoken.
• knowledge of another EU member state language is an asset.
• candidates must be eligible to work in the EU.